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[Multimedia Develop] h264_cabac

Description: The Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG are finalising a new standard for the coding (compression) of natural video images. The new standard [1] will be known as H.264 and also MPEG-4 Part 10, “Advanced Video Coding”. The standard specifies two types of entropy coding: Context-based Adaptive Binary Arithmetic Coding (CABAC) and Variable-Length Coding (VLC). This document provides a short introduction to CABAC. Familiarity with the concept of Arithmetic Coding is assumed (see chapter 8 of [2] for an introduction to Arithmetic Coding).-The Joint Video Team (JVT) of ISO/IEC MPEG and the ITU-T JTC 1 are Finalizing a new standard for the coding (compression) of natural video images. The new standard [1] will be known as H.264 and MPEG also-4 Part 10, "Advanced Video Coding." The standard specifies two types of entropy coding : Context-based Adaptive Binary Arithmetic Coding (CABAC) and Variable-Length Coding (VLC). This document provides a short introduction to CABAC. Familiarity with the concept of Arithmetic Coding is assumed (see chapter 8 of [2] for an introduction to Arithmetic Coding).
Platform: | Size: 14336 | Author: lucy | Hits:

[ARM-PowerPC-ColdFire-MIPS] 第1章－SD卡读写模块

Description: 第1章－SD卡读写模块 1. sdconfig.h: 该文件为SD卡读写模块配置头文件，用户可根据实际硬件条件进行修改. 2. SD目录 : SD卡读写模块的全部文件,一般不用修改. 3. 建议sdconfig.h文件不要放于SD目录中，因为SD目录中的文件一般无须修改,sdconfig.h通常会有改动. 4. 例子见上一级目录的SDExample目录.-Chapter 1-SD Card Reader module 1. Sdconfig.h : This document SD Card Reader module configuration files, users can be based on actual hardware changes. 2. SD Contents : SD Card Reader module all documents, generally need not be amended. 3. Recommendations sdconfig.h documents will not put SD directory because the directory SD generally no need to amend the document, sdconfig.h usually subject to change. 4. See above examples SDExample a directory of directories.
Platform: | Size: 168960 | Author: k14789 | Hits:

[VHDL-FPGA-Verilog] FIR31

Description: 设计一个线性相位FIR滤波器（31阶） 输入8位，输出8位,H(n)={1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69,111,128,111,……2,1} H(n)具有对称性。 输入信号范围 [±99，0，0，0， ±70，0，0，0， ±99，0，0，0， ±70，…]-Design a linear phase FIR filter (31 bands) 8 input, 8 output, H (n) = (1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69111128111, ... ... 2,1) H (n) has a symmetry. Input signal range [± 99,0,0,0, ± 70,0,0,0, ± 99,0,0,0, ± 70, ...]
Platform: | Size: 2641920 | Author: 陈金立 | Hits:

[Books] H.264

Description: h.264文档学习，参考资料，比较全，内容新-h.264 document learning, reference, compare the whole, the contents of the new
Platform: | Size: 3219456 | Author: xialw | Hits:

[MiddleWare] X-HDL3.2.52

Description: VHDL与VerilogHDL语言之间相互转换-VHDL language and VerilogHDL conversion between
Platform: | Size: 3958784 | Author: 高 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。 使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[VHDL-FPGA-Verilog] x_hdl

Description:
Platform: | Size: 4027392 | Author: navy | Hits:

[VHDL-FPGA-Verilog] freq

Description: 智能频率计 1. 频率测量范围为1Hz~1MHz 2. 当频率在1KHz以下时采用测周方法 其它情　　 　　况采用测频方法.二者之间自动转换 3. 测量结果显示在数码管上,单位可以是Hz（Ｈ）、　 　　KHz（ＡＨ）或MHz（ＢＨ）。 ４. 测量过程不显示数据，待测量结果结束后，直接显示结果。 -Intelligent frequency meter 1. Frequency measurement range of 1Hz ~ 1MHz 2. When the frequency of 1KHz weeks following measurement methods used in other circumstances the use of frequency measurement methods. Automatically switch between the two 3. Measurement results have shown that in the digital control, the unit can be Hz (H), KHz (AH) or MHz (BH). 4. Measurement process does not display data until after the end of the measurement results, the direct result will be displayed.
Platform: | Size: 238592 | Author: 谭超 | Hits:

[OS program] vh2sc

Description: 将VHDL转换为C的软件 将VHDL转换为C的软件-VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_int/sc_uint/integers and booleans this in order to maximise performance. The aim of the converter is to produce a cycle accurate model of synthesisable VHDL code. The converter runs on Windows Example1: Simple counter Convert the counter.vhd file to SystemC, c:VHDL2SystemCexample1>vh2sc-v-mti count.vhd VH2SC-> VHDL to SystemC Converter Ver 0.21** Alpha Release** (c)HT-Lab 2007 SQLite Version : 3.3.13 Parsing File : count.vhd Line 9** Info : library ieee ignored Line 28** Info : VH2SC Translation Disabled Line 32** Info : VH2SC Translation Re-Enabled Line 37** Info : process() translated to process_line37 Writing Header File : cnt.h Writing C++ File : cnt.cpp ** Info : Modelsim SC_MODULE_EXPORT(cnt) macro added The-v is a verbose flag and-mti is requi
Platform: | Size: 819200 | Author: whiz | Hits:

[Streaming Mpeg4] H.264

Description: H.264视频编解码程序，此程序已经过测试能够运行-H.264
Platform: | Size: 6497280 | Author: liluming | Hits:

[Windows Develop] directshow-MUX-DEMUX

Description: H.264解码器ffmpeg完整优化代码包括PC和WindowsMobile版本-ffmpeg WindowsMobile directshow mux implement
Platform: | Size: 361472 | Author: gan yong | Hits:

[VHDL-FPGA-Verilog] altera_up_avalon_sd_card_interface

Description: 基于VHDL的SD卡IP核，Altera公司推出的大学计划！最新版本9.0-VHDL-based IP core of the SD card, Altera' s university program launched! The latest version 9.0
Platform: | Size: 264192 | Author: 兔子 | Hits:

[Driver Develop] driver_for_dm9000a

Description: driver for dm9000a test
Platform: | Size: 2738176 | Author: nam | Hits:

[2D Graphic] H.264Decoder

Description: H.264解码器，用verilog写成，可以在FPGA上实现baseline的264解码-H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding
Platform: | Size: 5109760 | Author: sunwind | Hits:

[VHDL-FPGA-Verilog] AnEfficientDouble-FilterHardwareArchitectureforH.2

Description: 在此提出了一種新穎的硬體結構 實時執行的自適應去塊效應 過濾過程中指定的H.264/AVC視頻編碼 標準。-In this paper,a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented.The deblocking filter is a computationally and data intensive tool resulting in an increased execution time of both the encoding and decoding processes.
Platform: | Size: 799744 | Author: 張哲銘 | Hits:

[VHDL-FPGA-Verilog] 8-Bit-Up-Counter-With-Load

Description: 8位计数器与负荷 -----------------------8位计数器与负荷 -8-Bit Up Counter With Load 1------------------------------------------------------- 2-- Design Name : up_counter_load 3-- File Name : up_counter_load.vhd 4-- Function : Up counter with load 5-- Coder : Deepak Kumar Tala (Verilog) 6-- Translator : Alexander H Pham (VHDL) 7-------------------------------------------------------
Platform: | Size: 5120 | Author: 王浩 | Hits:

[VHDL-FPGA-Verilog] X-HDL

Description: 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
Platform: | Size: 3962880 | Author: 邵文熙 | Hits:

[Compress-Decompress algrithms] CAVLE-h264

Description: 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used directly to comprehensive post
Platform: | Size: 604160 | Author: zhanglong | Hits:

[VHDL-FPGA-Verilog] intra4x4

Description: Intra4x4 in VHDL for H.264 encoder. this module work with 3 intra prediction mode
Platform: | Size: 1882112 | Author: Roohi | Hits:

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